1. Field of the Invention
The present invention relates generally to techniques for delaying a signal, and more particularly, to digital delay-locked loops.
2. Description of the Related Art
Integrated circuit microprocessors typically interface to off-chip memory circuits (e.g., synchronous dynamic random-access memory, i.e., ‘SDRAM’) that transmit a strobe clock and data to the microprocessor. The strobe and data signals transmitted by the memory transition at the same time, i.e., the strobe and data are edge-aligned. Data may be transmitted on both rising and falling edges of the strobe or clock. In order to sample data in the middle of the data valid region, an on-chip memory interface typically delays the strobe. The strobe delay may be implemented in digital circuitry by a delay line controlled by a delay-locked loop (DLL), (e.g., a digital DLL).
Digital DLLs typically include a digital delay line and a controller including digital logic gates. The controller provides a set of control bits to the digital delay line that is used to delay a clock signal. The controller determines if the delay of the delay line is more or less than a desired delay based on the clock signal and the delayed clock signal, and the controller adjusts the control bits accordingly. The result is a feedback system that continually calibrates a delay line to provide a specific delay on the integrated circuit across all process, voltage, and temperature (PVT) variations (e.g., fast or slow process, low or high supply voltage, hot or cold transistors, etc.).
The control bits for the DLL delay line (i.e., master line) correspond to a constant delay across PVT variations and can be used by the strobe delay line to provide a constant delay. Since the control bits correspond to a fixed amount of delay, (i.e., the period of the clock fed into the DLL), the control code is used by gear or ratio logic before being sent to the strobe or delay line (i.e., slave line). The gear logic typically performs mathematical operations on the control bits to determine a desired delay for the strobe delay line and corresponding control signals for the strobe delay line. Due to the complexity of implementing mathematical operations, the gear logic may consume significant amounts of integrated circuit area. Accordingly, improved techniques for generating signals controlling a delay of a strobe delay line are desired.